With reference to FIGS. 5 and 6, a conventional sensor and a driving method thereof will be described. FIG. 5 is a circuit diagram of a conventional sensor. The sensor shown in FIG. 5 has photosensitive cells (the portions surrounded by dotted-lines) arranged in a 2×2 matrix form. Each photosensitive cell includes a photodiode 51, a transfer gate 52, a floating diffusion layer portion 53, an amplifying transistor 54, a reset transistor 55, and an address transistor 56, and corresponds to one of the pixels composing an image. Note that although the following description will assume, for simplicity, that the photosensitive cells are arranged in a 2×2 matrix form, in practice, several tens to several thousands of photosensitive cells are arranged in each of the row and column directions.
A method of driving the sensor shown in FIG. 5 is as follows. To extract signals from photosensitive cells in the first row, first, address transistors 56a and 56b included in the photosensitive cells in the first row are controlled to be in an ON state by a vertical shift register 61. Then, reset transistors 55a and 55b are similarly controlled to be in an ON state by the vertical shift register 61. This resets floating diffusion layer portions 53a and 53b. At this stage, an amplifying transistor 54a and a load transistor 63p form a source follower circuit, and an output from the source follower circuit appears on a vertical signal line 62p. Similarly, an amplifying transistor 54b and a load transistor 63q form a source follower circuit, and an output from the source follower circuit appears on a vertical signal line 62q as well. Voltages appearing on the vertical signal lines 62p and 62q at this stage are noise voltages which are unrelated to signal charges accumulated in photodiodes 51a and 51b. Subsequently, transfer gates 52a and 52b are controlled to be in an ON state by the vertical shift register 61. By this, the signal charges accumulated in the photodiodes 51a and 51b are transferred to the floating diffusion layer portions 53a and 53b, and signal voltages corresponding to the signal charges accumulated in the photodiodes 51a and 51b appear on the vertical signal lines 62p and 62q. 
Clamp capacitors 64p and 64q, clamp transistors 65p and 65q, sample/hold transistors 66p and 66q, and sample/hold capacitors 67p and 67q form a noise suppression circuit. The noise suppression circuit determines the difference between a pixel output obtained when there are signal charges in the floating diffusion layer portions 53 (i.e., a signal output) and a pixel output obtained when there is no signal charge (i.e., a noise output). In the sensor shown in FIG. 5, mainly, noise caused by variations in the threshold voltages of the amplifying transistors 54 and kTC noise which is the thermal noise of the reset transistors 55 are generated. When noise outputs are appearing on the vertical signal lines 62p and 62q, the clamp transistors 65p and 65q and the sample/hold transistors 66p and 66q are controlled to be in an ON state through control terminals 74 and 75, and a noise-free clamp voltage is applied to the sample/hold capacitors 67p and 67q from a clamp voltage supply terminal 73. After a predetermined time has elapsed, the clamp transistors 65p and 65q are controlled to be in an OFF state through the control terminal 74.
Subsequently, a voltage equal to the sum of a noise-free signal voltage and a noise voltage appears on each of the vertical signal lines 62p and 62q. The vertical signal lines 62p and 62q each change from the noise voltage to the sum of the signal voltage and the noise voltage; the amount of the change is equal to the noise-free signal voltage. Therefore, the voltage of each of the clamp capacitors 64p and 64q on the sample/hold side also changes by an amount equal to the noise-free signal voltage. In practice, the voltage across each of the sample/hold capacitors 67p and 67q changes from the noise-free clamp voltage by an amount obtained by dividing the amount of signal voltage change on the corresponding vertical signal line 62p or 62q by a corresponding clamp capacitor and a corresponding sample/hold capacitor. Therefore, the voltage across each of the sample/hold capacitors 67p and 67q is the noise-free clamp voltage and the divided signal voltage, and the noise portion is removed. After the sample/hold transistors 66p and 66q are controlled to be in an OFF state, horizontal transistors 68p and 68q are sequentially and selectively controlled to be in an ON state by a horizontal shift register 69. By this, signals corresponding to the signal charges accumulated in the photodiodes 51a and 51b are sequentially outputted from an output terminal 70.
Next, to extract signals from photosensitive cells in the second row, the same operations as for the first row are performed on the photosensitive cells in the second row. By this, signals corresponding to signal charges accumulated in photodiodes 51c and 51d are sequentially outputted from the output terminal 70.
A timing chart showing the above-described operations is as shown in FIG. 6. In FIG. 6, the period during which signals accumulated in photodiodes 51 for one row are finally outputted from the output terminal 70 is called a horizontal effective period, and the period during which the signals are outputted from the photodiodes 51 to the vertical signal lines 62 and the noise of the outputted signals is suppressed is called a horizontal blanking period. The horizontal blanking period and the horizontal effective period are together called one horizontal period. The one horizontal period is the time actually required to read signals for one row. The time required to read signals from the entire sensor is called one frame period. As shown in FIG. 6, the amount of a signal charge accumulated in the photodiode 51 is determined by the time interval of a transfer pulse to be applied to the transfer gate 52. The time interval of the transfer pulse is constant during one frame period. Therefore, the photodiodes 51 have uniform sensitivity.
In the sensor shown in FIG. 5, each photosensitive cell is composed of four transistors (a transfer gate 52, an amplifying transistor 54, a reset transistor 55, and an address transistor 56). On the other hand, in recent years, for reduction in size of sensors, there has developed a sensor having photosensitive cells each composed of three transistors. This newly developed sensor has a configuration in which address transistors 56 are removed from the sensor shown in FIG. 5 and the power supply is shared between the photosensitive cells. In order to read signals from this sensor, it is necessary to supply a pulsed power supply voltage to each photosensitive cell.
A method of driving the sensor shown in FIG. 5 is described in Japanese Laid-Open Patent Publication No. 9-247537, for example. In addition, Japanese Laid-Open Patent Publication No. 2001-45375 describes a driving method by which signals from photodiodes for one row are averagely outputted in one horizontal period.
However, in the sensor in which each photosensitive cell is composed of three transistors, because the power supply is pulse-driven, problems such as those described below may arise. First, since the power supply is connected to all the photosensitive cells and not only a selected photosensitive cell but the entire sensor is driven, adverse effects are exerted on the operation of the entire sensor. Secondly, although the power supply voltage at a high level does not exert adverse effects on the operation of the sensor, the power supply voltage at a low level exerts adverse effects on the operation of a non-selected photosensitive cell. Thirdly, pulse-driving of the power supply per se exerts various adverse effects on the entire sensor.
In particular, in terms of the aforementioned second problem, if the low-level potential of the power supply becomes too low, this low-level potential may become equal to or lower than the low-level potential of the reset transistors of non-selected photosensitive cells and reach even to the gate regions of amplifying transistors. Here, a large number of amplifying transistors simultaneously go into operation and drive the entire sensor. Accordingly, a great noise is superimposed during a horizontal blanking period, and thereby signal processing becomes difficult.
If the low-level potential of the power supply becomes equal to or lower than the low-level potential of the transfer gates of non-selected photosensitive cells, charges are injected into photodiodes, causing variations in the amount of charge injected into the photosensitive cells. Accordingly, variations occur in signal charges to be read from the photodiodes and thereby a great noise appears in a reproduced image.
Therefore, an object of the present invention is to provide a method of driving a solid-state imaging device, by which a reproduced image with low noise is read from a sensor having photosensitive cells each composed of three transistors.